$date
	Wed Jan 17 19:36:41 2024
$end
$version
	Icarus Verilog
$end
$timescale
	100ps
$end
$scope module m_top $end
$scope module m $end
$var wire 1 ! w_clk $end
$var wire 1 " w_in $end
$var wire 1 # w_out $end
$var reg 4 $ r_s [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 $
0#
1"
0!
$end
#2000
b1000 $
1!
#2500
0!
#3000
b1100 $
1!
#3500
0!
#4000
b1110 $
1!
#4500
0!
#5000
1#
b1111 $
1!
#5500
0!
#6000
1!
#6500
0!
#7000
1!